Proper latching of bit 7 on $4201

zsnes/src/cpu/regs.inc

@@ -665,9 +665,10 @@ NEWSYM vramread2, db 0             ; previous character for vram read
 NEWSYM nosprincr, db 0
 NEWSYM poamaddrs, dw 0
 NEWSYM ioportval, db 0
+NEWSYM iohvlatch, db 0
 
 
-NEWSYM tempdat, times 479 db 0     ; expandable area
+NEWSYM tempdat, times 478 db 0     ; expandable area
 
 num2writeppureg equ $-sndrot
 ; pharos equ hack *sigh*
@@ -767,8 +768,11 @@ reg2137r:
 ;    mov byte[debstop3],1
     cmp byte[debuggeron],1
     je .debugger
+    cmp byte[iohvlatch],1
+    je .dolatch
     test byte[ioportval],80h
     jnz .nolatch
+.dolatch
     xor ebx,ebx
     mov bl,[cycpl]
     sub bl,dh
@@ -794,8 +798,11 @@ reg2137r:
     ret
 .debugger
 debblah:
+    cmp byte[iohvlatch],1
+    je .dolatch2
     test byte[ioportval],80h
     jnz .nolatch2
+.dolatch2
     xor ebx,ebx
     mov bl,[cycpl]
     sub bl,[pdh]

zsnes/src/cpu/regsw.inc

@@ -1504,6 +1504,18 @@ reg4200w:
 
 ; Programmable I/O port (out-port)
 reg4201w:
+    cmp byte[iohvlatch],1
+    jne .noiohvlatch
+    test al,80h
+    jnz .noiohvlatch
+    mov byte[iohvlatch],0
+.noiohvlatch
+    test byte[ioportval],80h
+    jnz .nolatch
+    test al,80h
+    jz .nolatch
+    mov byte[iohvlatch],1
+.nolatch
     mov byte[ioportval],al
     mov bl,al
     and bl,80h