Cleaned up mapping.
This commit is contained in:
n-a-c-h
@@ -32,6 +32,7 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#include <sys/stat.h>
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#define DIR_SLASH "\\"
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#endif
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#include "cpu/memtable.h"
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#include "zip/zunzip.h"
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#include "jma/zsnesjma.h"
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#include "asm_call.h"
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@@ -1937,20 +1938,6 @@ void InitDSP(), InitDSP2(), InitDSP4(), InitFxTables(), initregr(), initregw();
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void SPC7110Load();
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void rep_stosd(void (**fptrarray)(), void (*fptr), unsigned int);
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extern void (*memtabler8[256])(), (*memtablew8[256])();
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extern void (*memtabler16[256])(), (*memtablew16[256])();
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void sramaccessbankr8(), sramaccessbankw8(), DSP4Read8b(), DSP4Write8b();
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void sramaccessbankr16(), sramaccessbankw16(), DSP4Read16b(), DSP4Write16b();
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void sfxaccessbankr8(), sfxaccessbankw8(), sfxaccessbankr16(), sfxaccessbankw16();
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void sfxaccessbankr8b(), sfxaccessbankw8b(), sfxaccessbankr16b(), sfxaccessbankw16b();
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void sfxaccessbankr8c(), sfxaccessbankw8c(), sfxaccessbankr16c(), sfxaccessbankw16c();
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void sfxaccessbankr8d(), sfxaccessbankw8d(), sfxaccessbankr16d(), sfxaccessbankw16d();
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void sramaccessbankr8s(), sramaccessbankw8s(), sramaccessbankr16s(), sramaccessbankw16s();
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void setaaccessbankr8(), setaaccessbankw8(), setaaccessbankr16(), setaaccessbankw16();
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void setaaccessbankr8a(), setaaccessbankw8a(), setaaccessbankr16a(), setaaccessbankw16a();
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void DSP1Read8b3F(), DSP1Write8b3F(), DSP1Read16b3F(), DSP1Write16b3F();
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void DSP2Read8b(), DSP2Write8b(), DSP2Read16b(), DSP2Write16b();
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void CheckROMTypeC()
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{
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unsigned char *ROM = (unsigned char *)romdata;
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@@ -1959,75 +1946,56 @@ void CheckROMTypeC()
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MirrorROM();
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lorommapmode2 = 0;
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if (!strncmp(ROM+0x207FC0, "DERBY STALLION 96", 17)) { lorommapmode2 = 1; }
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if (!strncmp(ROM+0x7FC0, "SOUND NOVEL-TCOOL", 17)) { lorommapmode2 = 1; }
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if (!strncmp(ROM+0x207FC0, "DERBY STALLION 96", 17) || !strncmp(ROM+Lo, "SOUND NOVEL-TCOOL", 17))
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{
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lorommapmode2 = 1;
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}
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// Setup memmapping
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SetAddressingModes();
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GenerateBank0Table();
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chip_detect();
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disablespcclr = (memcmp(ROM+0xFFC0, "\0x42\0x53\0x20\0x5A", 4)) ? 0 : 1;
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disablespcclr = (memcmp(ROM+Hi, "\0x42\0x53\0x20\0x5A", 4)) ? 0 : 1;
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if ((romtype == 1) && (!SDD1Enable))
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{ // Non-SDD1 LoROM SRAM mapping, banks F0 - F3
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rep_stosd(memtabler8+0xF0, sramaccessbankr8, 4);
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rep_stosd(memtablew8+0xF0, sramaccessbankw8, 4);
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rep_stosd(memtabler16+0xF0, sramaccessbankr16, 4);
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rep_stosd(memtablew16+0xF0, sramaccessbankw16, 4);
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map_mem(0xF0, &srambank, 4);
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}
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// Setup DSP-X stuff
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DSP1Type = 0;
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if (DSP1Enable || DSP2Enable || DSP3Enable)
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if (DSP1Enable || DSP2Enable || DSP3Enable)
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{
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if (DSP2Enable) { asm_call(InitDSP2); }
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if (DSP2Enable) { asm_call(InitDSP2); }
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InitDSP();
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DSP1Type = (romtype == 2) ? 2 : 1;
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}
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if (DSP4Enable)
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{ // DSP-4 mapping, banks 30 - 3F
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{
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InitDSP4();
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rep_stosd(memtabler8+0x30, DSP4Read8b, 0x10);
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rep_stosd(memtablew8+0x30, DSP4Write8b, 0x10);
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rep_stosd(memtabler16+0x30, DSP4Read16b, 0x10);
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rep_stosd(memtablew16+0x30, DSP4Write16b, 0x10);
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// DSP-4 mapping, banks 30 - 3F
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map_mem(0x30, &dsp4bank, 0x10);
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}
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if (SFXEnable)
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{ // Setup SuperFX stuff
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{
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// Setup SuperFX stuff
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if (Sup48mbit)
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{
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// banks 70
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memtabler8[0x70] = sfxaccessbankr8;
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memtablew8[0x70] = sfxaccessbankw8;
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memtabler16[0x70] = sfxaccessbankr16;
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memtablew16[0x70] = sfxaccessbankw16;
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// banks 71
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memtabler8[0x71] = sfxaccessbankr8b;
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memtablew8[0x71] = sfxaccessbankw8b;
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memtabler16[0x71] = sfxaccessbankr16b;
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memtablew16[0x71] = sfxaccessbankw16b;
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// banks 72
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memtabler8[0x72] = sfxaccessbankr8c;
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memtablew8[0x72] = sfxaccessbankw8c;
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memtabler16[0x72] = sfxaccessbankr16c;
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memtablew16[0x72] = sfxaccessbankw16c;
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// banks 73
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memtabler8[0x73] = sfxaccessbankr8d;
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memtablew8[0x73] = sfxaccessbankw8d;
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memtabler16[0x73] = sfxaccessbankr16d;
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memtablew16[0x73] = sfxaccessbankw16d;
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// banks 78 - 79
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rep_stosd(memtabler8+0x78, sramaccessbankr8s, 2);
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rep_stosd(memtablew8+0x78, sramaccessbankw8s, 2);
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rep_stosd(memtabler16+0x78, sramaccessbankr16s, 2);
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rep_stosd(memtablew16+0x78, sramaccessbankw16s, 2);
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//SuperFX mapping, banks 70 - 73
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map_mem(0x70, &sfxbank, 1);
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map_mem(0x71, &sfxbankb, 1);
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map_mem(0x72, &sfxbankc, 1);
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map_mem(0x73, &sfxbankd, 1);
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//SRAM mapping, banks 78 - 79
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map_mem(0x78, &sramsbank, 2);
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SfxR1 = 0;
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SfxR2 = 0;
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memset(sfxramdata, 0, 262144); // clear 256kB SFX ram
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@@ -2046,24 +2014,24 @@ void CheckROMTypeC()
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}
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if (SETAEnable)
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{ // Setup SETA 010/011 stuff
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{
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// Setup SETA 010/011 stuff
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// Really banks 68h-6Fh:0000-7FFF are all mapped the same by the chip but
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// F1 ROC II only uses bank 68h
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memtabler8[0x68] = setaaccessbankr8;
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memtablew8[0x68] = setaaccessbankw8;
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memtabler16[0x68] = setaaccessbankr16;
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memtablew16[0x68] = setaaccessbankw16;
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map_mem(0x68, &setabank, 1);
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// Control register (and some status?) is in banks 60h-67h:0000-3FFF
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memtabler8[0x60] = setaaccessbankr8a;
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memtablew8[0x60] = setaaccessbankw8a;
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memtabler16[0x60] = setaaccessbankr16a;
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memtablew16[0x60] = setaaccessbankw16a;
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map_mem(0x60, &setabanka, 1);
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SetaCmdEnable = 0x00000080; // 60:0000
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memset(setaramdata, 0, 4096); // clear 4kB SETA ram
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// proper SETA sram area
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if (SramExists) { memcpy(setaramdata, sram, 4096); }
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if (SramExists)
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{
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memcpy(setaramdata, sram, 4096);
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}
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}
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// General stuff all mixed together [... wouldn't it be cool to clean that]
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@@ -2088,27 +2056,13 @@ void CheckROMTypeC()
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if (DSP1Type == 1)
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{
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rep_stosd(memtabler8+0x30, DSP1Read8b3F, 0x10);
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rep_stosd(memtablew8+0x30, DSP1Write8b3F, 0x10);
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rep_stosd(memtabler16+0x30, DSP1Read16b3F, 0x10);
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rep_stosd(memtablew16+0x30, DSP1Write16b3F, 0x10);
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rep_stosd(memtabler8+0xB0, DSP1Read8b3F, 0x10);
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rep_stosd(memtablew8+0xB0, DSP1Write8b3F, 0x10);
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rep_stosd(memtabler16+0xB0, DSP1Read16b3F, 0x10);
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rep_stosd(memtablew16+0xB0, DSP1Write16b3F, 0x10);
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rep_stosd(memtabler8+0xE0, DSP1Read8b3F, 0x10);
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rep_stosd(memtablew8+0xE0, DSP1Write8b3F, 0x10);
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rep_stosd(memtabler16+0xE0, DSP1Read16b3F, 0x10);
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rep_stosd(memtablew16+0xE0, DSP1Write16b3F, 0x10);
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map_mem(0x30, &dsp1bank, 0x10);
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map_mem(0xB0, &dsp1bank, 0x10);
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map_mem(0xE0, &dsp1bank, 0x10);
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if (DSP2Enable)
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{
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memtabler8[0x3F] = DSP2Read8b;
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memtablew8[0x3F] = DSP2Write8b;
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memtabler16[0x3F] = DSP2Read16b;
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memtablew16[0x3F] = DSP2Write16b;
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map_mem(0x3F, &dsp2bank, 1);
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}
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}
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